• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Providing a first layer 20 of silicon oxide by oxidation on the surface 9 of the silicon bodies 1, 2, forming a base region 21 by ion implantation, and Forming a second layer 22 of silicon oxide by vapor deposition on one layer, forming a window 26 in which the surface of the silicon body is exposed in the two layers of silicon oxide, and a second layer of silicon oxide Depositing a layer of polycrystalline silicon in the window on the window and forming the emitter region 29 through diffusion of the dopant from the layer of polycrystalline silicon in the base region. A device manufacturing method is disclosed. Before the layer of polycrystalline silicon is deposited, a top protective layer 23 resistant to the cleaning liquid containing HF is deposited on the second layer of silicon oxide. Thus, conventional HF immersion treatment can be performed before the layer of polycrystalline silicon is deposited, without the bipolar transistors in the integrated circuits exhibiting very different electrical properties as a result.
    公开号:KR20000070028A
    申请号:KR1019997006247
    申请日:1998-10-19
    公开日:2000-11-25
    发明作者:반데르미르핸드리크후베르투스；멀피윌리암마르크；피터스베.체.엠.；포스트마포케
    申请人:요트.게.아. 롤페즈；코닌클리케 필립스 일렉트로닉스 엔.브이.；
    IPC主号:
    专利说明:

    Manufacture method of a semiconductor device having a poly-emitter bipolar transistor
    In particular, this method is suitable for combining with methods of manufacturing semiconductor devices, such as integrated circuits, including MOS transistors. At this time, bipolar transistors can be included in these MOS circuits by adding only a few processes.
    In this method, the base region of the bipolar transistor is formed through the implantation of dopant ions. This implantation is carried out through the first layer of silicon oxide. This silicon oxide layer formed through the oxidation of silicon can be formed to a precisely defined thickness. Thus, the base region formed by implantation has a precisely defined depth. As is common, if this semiconductor device has so many bipolar transistors, the base of all of these transistors will have some constant depth.
    The emitter of a bipolar transistor is formed through the diffusion of dopants from a layer of polycrystalline silicon provided in a window. This layer may be provided with a dopant during or after deposition, for example through implantation of related dopant ions. The second layer of silicon oxide indicates that a capacitor with only low capacitance is formed between the base region and the layer of polycrystalline silicon on the second layer of silicon oxide so that the transistor is suitable for processing high frequency signals. To ensure.
    A method of the type mentioned at the outset is known from US Pat. No. 5,171,702, wherein the second layer of silicon oxide is a layer deposited from a gas comprising tetraethoxysilane (TEOS). The layer of polycrystalline silicon is deposited directly on the second layer of silicon oxide in the window. The window is etched in the plasma formed at CHF 3 , C 2 F 6 and He, where the mixed silicon oxide can be selectively etched against the single crystal silicon of the silicon body.
    Indeed, in the manufacture of integrated circuits having a plurality of bipolar transistors thus produced, it is found that bipolar transistors in such circuits sometimes exhibit very different characteristics. In particular, high frequency signals may be amplified differently by individual transistors.
    The present invention is a method for manufacturing a semiconductor device having a bipolar transistor,
    Providing a first layer of silicon oxide by oxidation on the surface of the silicon body;
    Forming a base region by ion implantation;
    Forming a second layer of silicon oxide by vapor deposition on the first layer of silicon oxide;
    Forming a window in the two layers of silicon oxide to expose the surface of the silicon body;
    Depositing a layer of polycrystalline silicon in the window on the second layer of silicon oxide;
    A method of manufacturing a semiconductor device comprising forming an emitter region through diffusion of a dopant from a layer of polycrystalline silicon in a base region.
    1 to 5 are schematic cross-sectional views showing several steps in the manufacture of a semiconductor device in which the method according to the invention is used.
    The object of the present invention is to overcome this disadvantage. According to the invention, for this purpose, the method is characterized in that a top protective layer resistant to the cleaning liquid containing HF is provided on the second layer of silicon oxide before the layer of polycrystalline silicon is deposited.
    Before the layer of polycrystalline silicon is deposited, a conventional "HF dip", such as a short etch treatment in an etchant containing HF, is actually performed. This is done for the purpose of removing impurities and oxidative residues which may be left on the silicon after the etching treatment of the window to the first and second layers of silicon oxide. However, it is found that the second layer of deposited silicon oxide may be strongly damaged locally due to such cleaning treatment, especially when deposited from a gas of tetraethoxysilane. As a result, this layer can exhibit significant local variation in thickness. With the second layer of silicon oxide forming the dielectric, the capacitor formed between the polycrystalline silicon and the base region can have different capacitance values for the individual transistors. Thus, high frequency signals may have different gains. The use of the top protective layer prevents the second layer of silicon oxide from being locally damaged during the HF immersion treatment. In fact it is found that the change in the properties of the individual bipolar transistors in the integrated circuit is greatly reduced by the use of the top layer.
    The top layer may be provided on the second layer of silicon oxide after the window is etched into the second layer of silicon oxide, but preferably, the top layer is provided on the second layer of silicon oxide before the window is formed. The window is then formed in two layers and the top layer of silicon oxide. In this way a simple method is obtained.
    Materials common to semiconductor technologies such as silicon nitride or monocrystalline or polycrystalline silicon may be used for the top layer. Preferably a layer of hydrophilic material is deposited as the top layer. It is found that when a hydrophobic top layer such as a layer of monocrystalline or polycrystalline silicon is used, relatively high contact resistance can occur between the layer of polycrystalline silicon and the emitter region of some transistors of an integrated circuit. As a result, low frequency signals can be amplified differently by various transistors. This is avoided when a hydrophilic top layer is used. The silicone body is rinsed with water after the HF dip treatment. Water rinsed by the silicon body after the HF immersion treatment may be left on the hydrophilic silicon oxide sidewalls of the window. If a hydrophilic top layer is used, water on the sidewall may flow along the top layer during drying, but this is not possible by the use of a hydrophobic top layer, and water will be left on the wall. The presence of water on the wall of the window allows the silicon to oxidize in the window during the deposition of polycrystalline silicon, which is carried out at virtually high temperatures. In this way a thin layer of silicon oxide can be created between the polycrystalline silicon and the emitter region.
    Preferably, a layer of silicon nitrate is deposited as the top layer. The layer of silicon nitrate is hydrophilic. In addition, such a layer does not cause problems during the etching of the window and during the etching of the layer of polycrystalline silicon into the pattern. The window can be etched in a plasma that etches the top layer of silicon nitrate and the two layers of silicon oxide very selectively to silicon, so that the silicon in the window is not actually damaged during the etching of the window. Patterning of the layer of polycrystalline silicon by etching, such that the connecting electrode of the emitter is formed, can be performed so that the polycrystalline silicon and silicon nitrate are highly selective to the silicon oxide in the same plasma etching process. The second layer of silicon oxide is not actually damaged during the patterning of the layer of polycrystalline silicon.
    Hereinafter, the present invention will be described in more detail by way of example with reference to the drawings.
    1 to 5 are schematic cross-sectional views illustrating several steps in the fabrication of semiconductor devices, i.e., integrated circuits with NMOS and PMOS transistors, in which the method according to the invention is used for incorporating bipolar transistors in this circuit. . Such a circuit may have many such transistors, but for the sake of simplicity of drawing only one of these transistors is shown.
    This embodiment starts with the state shown in FIG. A relatively low doped n-type layer 2 at about 8 * 10 15 atoms per cc has been epitaxially grown on the wafer 1 with silicon. A relatively doped n-type buried layer 3 at about 10 19 atoms per cc, into which a bipolar transistor would be formed, was formed in a conventional manner. A p-type region 4 having a doping concentration of about 5 * 10 16 atoms per cc, where NMOS transistors are to be formed, was provided via ion implantation. The regions 5, 6 and 7 in which the NMOS, PMOS and bipolar transistors respectively are to be formed are insulated from each other by the field insulating regions 8 in a conventional manner.
    A layer of gate oxide 10 having a thickness of about 12 nm is formed on the surface 9 of the active regions 5, 6, 7. Next, a layer of polycrystalline silicon is deposited in a conventional manner, where a gate electrode 11 for the NMOS transistor and a gate electrode 12 for the PMOS transistor are formed. Relatively low doped n-type source and drain regions 13 and P-type source and drain regions 14 are formed by gate electrodes 11 and 12 through ion implantation having about 5 * 10 17 atoms per cc. Next, the side surfaces of the gate electrodes 11 and 12 are provided with an insulating strip (spacer) 15 of silicon oxide in a conventional manner. During this process the surfaces on the active regions 5, 6, 7 mixed with the gate electrodes 11 and 12 by the side surfaces 15 are exposed.
    Finally, relatively highly doped connection regions are formed by ion implantation having about 10 19 atoms per cc, which are n-type regions 16 for NMOS transistors. FIG. 1 shows a step in which a p-type connection region 17 for a PMOS transistor and a p-type connection region 18 for a bipolar transistor are simultaneously formed. The active region for the NMOS transistor is covered with a photoresist mask 19 for this purpose. The same mask 19 also covers the portion of the active region 7 in which the base region 20 of the bipolar transistor is to be formed.
    The next processing step for manufacturing the bipolar transistor is the removal of the photoresist mask 19. Next, a first layer 20 of silicon oxide having a thickness of 12 nm is formed by oxidation of silicon. The base region 21 of the bipolar transistor is then formed by ion implantation through the layer 20. For this purpose, per cm 2 is injected into approximately 4 × 10 13 p-type ions (in this embodiment, boron ions) are all active region without the mask (5, 6, 7). In the heavily doped exposed areas 16, 17, 18, the doping level does not actually change. The base area 21 is formed between the connection areas 18. This results in the state shown in FIG.
    The first layer of silicon oxide 20 formed by oxidation of silicon can be formed to a precisely defined thickness. As a result, the base region 21 formed by implantation has a precisely defined depth. Thus, the depths of all base regions 21 of the bipolar transistors in the circuit will be the same.
    Next, as shown in FIG. 3, a second layer 22 of silicon oxide about 100 nm thick is provided, provided with a top layer 23 about 30 nm thick. A photoresist mask 24 having an opening 25 in which the emitter region of the bipolar transistor is to be formed is provided on the top layer 23 in a conventional manner. The window 26 on which the surface 9 of the silicon body is exposed is etched into layers 20 and 22 and top layer 23 of silicon oxide by an etching plasma. Window 26 has walls 27 abutting layers 20 and 22 of silicon oxide.
    Next, as shown in FIG. 4, a layer 28 of polycrystalline silicon is deposited over the top layer 23, over the second insulating layer 22, and in the window 26. This layer is provided with an n-type dopant such that vapor deposition of a gas mixture of dopants is carried out in the reaction chamber in which deposition takes place, or dopant ions are implanted into the layer after deposition. In this example, about 5 * 10 15 arsenic ions per cm 2 are implanted into the layer of polycrystalline silicon.
    An emitter region 29 is then formed in the base region 21 through diffusion of this dopant from the layer of polycrystalline silicon 28. Finally, emitter electrode 30 is formed in the layer of polycrystalline silicon 28. During this process, the top layer 23 is removed from the second layer of silicon oxide 22 to the emitter electrode.
    The use of two layers 20 and 22 and top layer 23 of silicon oxide achieves that a capacitor having only a low capacitance value is formed between emitter electrode 30 and base region 21. Thus, this transistor is suitable for processing high frequency signals.
    The top protective layer 23 is provided on the second layer of silicon oxide 22. This top layer is resistant to the cleaning liquid containing HF. Thus, it is achieved that the bipolar transistor has substantially the same electrical properties as in the case of the manufacture of an integrated circuit comprising a large number of such bipolar transistors. In particular, signals with high frequencies can be amplified to the same extent by individual transistors.
    Before the polycrystalline silicon 28 is deposited, a conventional HF immersion treatment, that is, a short etching treatment is performed in an etching solution containing HF, for example, an aqueous solution of HF of 1 to 5%. This is done for the purpose of removing impurities and oxidation residues remaining on the silicon after the etching treatment of the window 26. The deposited layer of silicon oxide can be strongly damaged locally by such cleaning treatment, especially when deposited from tetraethoxysilane. Layer 22 may exhibit significant local thickness variation when top protective layer 23 is not used. In fact, a thickness difference of 30% was measured. As a result, the capacitor formed between the polycrystalline silicon and the base region may have different capacitance values for different transistors. Therefore, the above-described difference can be caused. The use of top protective layer 23 ensures that the second layer of silicon oxide is not locally damaged during the HF immersion treatment. It is thus found that the difference in the characteristics between the individual bipolar transistors in the integrated circuit is greatly reduced.
    Also, without the protective layer 23, pinholes may be formed in the second layer 22 of silicon oxide during the HF immersion treatment. These pinholes may be filled with polycrystalline silicon that is subsequently deposited on the layer, so a short circuit will occur in the semiconductor device. In addition, the local thickness variation in the second layer 22 of silicon oxide may have the result that capacitors formed in the semiconductor device having this layer as a dielectric have different capacitance values. Such a capacitor is formed by, for example, an aluminum track and gate electrodes 11 and 12 to be provided on the second layer 22 of silicon oxide.
    The top layer 23 may be formed on the second layer of silicon oxide after the window 26 is etched into the layer 22, but preferably the top layer 23 is shown in the figure, as shown in the figure. It is provided on the second layer of silicon oxide before it is formed. In that case the window 26 is formed in two layers of silicon oxide 20 and 22 and top layer 23. In this way a simple method is obtained.
    A layer of material conventional in semiconductor technology such as silicon nitride or single crystal or polycrystalline silicon may be used for the top layer 23. Preferably, a layer of hydrophilic material is deposited as top layer 23. It is found that when a hydrophobic top layer such as a layer of monocrystalline or polycrystalline silicon is used, relatively large connection resistance can occur between the layer of polycrystalline silicon and the emitter region of some transistors in an integrated circuit. Also, low frequency signals may be amplified differently by individual transistors as a result. Here, a twofold difference in gain was found. This is prevented by the use of a hydrophilic top layer. The silicone body is rinsed with water after the HF immersion treatment. Water rinsed by the silicon body after the HF immersion treatment may be left on the hydrophilic silicon oxide wall 27 of the window 26. If a hydrophilic top layer is used, the water on the wall may flow through the top layer, which is not possible with the hydrophobic top layer and water will be left on the wall. The presence of water on the wall of the window allows the silicon to be oxidized inside the window during deposition of the layer 28 of polycrystalline silicon, which is performed at high temperature. As such, a thin layer of silicon oxide can result between the polycrystalline silicon and the emitter region.
    Preferably, a layer of silicon nitrate is deposited as top layer 23. The layer of silicon nitrate is hydrophilic. Also, such a layer does not cause any problems during the etching 26 of the window and during the etching of the emitter electrode 30 to the polycrystalline silicon 28. Window 26 may be etched in a plasma formed of a gas mixture comprising Ar, CF 4, and CHF 3 , which mixture comprises both top layer 23 of silicon nitrate and two layers 20 and 22 of silicon oxide. Since it is very selective to etch silicon, the silicon inside the window 26 is not actually damaged during the etching of the window 26. The etching of the emitter electrode 30 into the layer 28 of polycrystalline silicon can be performed in a plasma formed of a gas mixture comprising CL 2 and He, where the polycrystalline silicon 28 and silicon nitrate 23 are silicon It is selectively etched with respect to the oxide. The second layer 22 of silicon oxide is not actually damaged during this process.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A method of manufacturing a semiconductor device having a bipolar transistor,
    Providing a first layer of silicon oxide by oxidation on the surface of the silicon body;
    Forming a base region by ion implantation;
    Forming a second layer of silicon oxide by vapor deposition on the first layer of silicon oxide;
    Forming a window in the first layer and the second layer of silicon oxide to expose a surface of the silicon body;
    Depositing a layer of polycrystalline silicon in said window on said second layer of silicon oxide;
    10. A method of fabricating a semiconductor device, comprising forming an emitter region through diffusion of a dopant from the layer of polycrystalline silicon within the base region.
    Providing a top protective layer resistant to a cleaning liquid containing HF on the second layer of silicon oxide prior to depositing the layer of polycrystalline silicon.
    [2" claim-type="Currently amended] 2. The top layer of claim 1, wherein the top layer is provided on the second layer of silicon oxide before the window is formed, wherein the window is formed in the first and second layers and the top layer of the silicon oxide. A semiconductor device manufacturing method.
    [3" claim-type="Currently amended] A method according to claim 1 or 2, wherein a layer of hydrophilic material is deposited as the top layer.
    [4" claim-type="Currently amended] 4. A method according to claim 3, wherein a layer of silicon nitrate is deposited as the top layer.
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    同族专利:
    公开号 | 公开日
    WO1999025003A2|1999-05-20|
    WO1999025003A3|1999-07-29|
    JP2001508242A|2001-06-19|
    EP0965144A2|1999-12-22|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-11-12|Priority to EP97203518.2
    1997-11-12|Priority to EP97203518
    1998-10-19|Application filed by 요트.게.아. 롤페즈, 코닌클리케 필립스 일렉트로닉스 엔.브이.
    2000-11-25|Publication of KR20000070028A
    优先权:
    申请号 | 申请日 | 专利标题
    EP97203518.2|1997-11-12|
    EP97203518|1997-11-12|
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